? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14517b/d mc14517b dual 64-bit static shift register the mc14517b dual 64bit static shift register consists of two identical, independent, 64bit registers. each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. data at the data input is entered by clocking, regardless of the state of the write enable input. an output is disabled (open circuited) when the write enable input is high. during this time, data appearing at the data input as well as the 16bit, 32bit, and 48bit taps may be entered into the device by application of a clock pulse. this feature permits the register to be loaded with 64 bits in 16 clock periods, and also permits bus logic to be used. this device is useful in time delay circuits, temporary memory storage circuits, and other serial shift register applications. ? diode protection on all inputs ? fully static operation ? output transitions occur on the rising edge of the clock pulse ? exceedingly slow input transition rates may be applied to the clock input ? 3state output at 64thbit allows use in bus logic applications ? shift registers of any length may be fully loaded with 16 clock pulses ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range maximum ratings (voltages referenced to v ss ) (note 1.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 2.) 500 mw t a operating temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 1. maximum ratings are those values beyond which damage to the device may occur. 2. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14517bcp pdip16 2000/box mc14517bdw soic16 47/rail marking diagrams 1 16 pdip16 p suffix case 648 mc14517bcp awlyyww mc14517bdwr2 soic16 1000/tape & reel soic16 dw suffix case 751g 1 16 14517b awlyyww
mc14517b http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 c b we b q48 b q16 b v dd d b q32 b q64 b c a we a q48 a q16 a v ss q32 a q64 a d a functional truth table (x = don't care) clock write enable data 16bit tap 32bit tap 48bit tap 64bit tap 0 0 x content of 16bit displayed content of 32bit displayed content of 48bit displayed content of 64bit displayed 0 1 x high impedance high impedance high impedance high impedance 1 0 x content of 16bit displayed content of 32bit displayed content of 48bit displayed content of 64bit displayed 1 1 x high impedance high impedance high impedance high impedance 0 data entered into 1st bit content of 16bit displayed content of 32bit displayed content of 48bit displayed content of 64bit displayed 1 data entered into 1st bit data at tap entered into 17bit data at tap entered into 33bit data at tap entered into 49bit high impedance 0 x content of 16bit displayed content of 32bit displayed content of 48bit displayed content of 64bit displayed 1 x high impedance high impedance high impedance high impedance
mc14517b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (3.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current (4.) (5.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (4.2 m a/khz) f + i dd i t = (8.8 m a/khz) f + i dd i t = (13.7 m a/khz) f + i dd m adc threestate leakage current i tl 15 e 0.1 e 0.0001 0.1 e 3.0 m adc 3. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 4. the formulas given are for the typical characteristics only at 25 c. 5. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.004.
mc14517b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (6.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ (7.) max unit output rise and fall time t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.65 ns/pf) c l + 9.5 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time t plh , t phl = (1.7 ns/pf) c l + 390 ns t plh , t phl = (0.66 ns/pf) c l + 177 ns t plh , t phl = (0.5 ns/pf) c l + 115 ns t plh , t phl 5.0 10 15 e e e 475 210 140 770 300 215 ns clock pulse width t wh 5.0 10 15 330 125 100 170 75 60 e e e ns clock pulse frequency f cl 5.0 10 15 e e e 3.0 6.7 8.3 1.5 4.0 5.3 mhz clock pulse rise and fall time t tlh , t thl 5.0 10 15 see note (8.) e data to clock setup time t su 5.0 10 15 0 10 15 40 15 0 e e e ns data to clock hold time t h 5.0 10 15 150 75 35 75 25 10 e e e ns write enable to clock setup time t su 5.0 10 15 400 200 110 170 65 50 e e e ns write enable to clock release time t rel 5.0 10 15 380 180 100 160 55 40 e e e ns 6. the formulas given are for the typical characteristics only at 25 c. 7. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 8. when shift register sections are cascaded, the maximum rise and fall time of the clock input should be equal to or less than th e rise and fall time of the data outputs, driving data inputs, plus the propagation delay of the output driving stage. figure 1. power dissipation test circuit and waveform c l c l c l c l c l c l c l c l v dd q16 q32 q48 q64 q16 q32 q48 q64 v dd v dd v ss v ss d c we d c we v ss i d d c 50 m f repetitive waveform c d f o (f = 1/2 f o )
mc14517b http://onsemi.com 5 figure 2. typical output source current characteristics test circuit figure 3. typical output sink current characteristics test circuit external power supply i oh v out = v oh v dd = v gs v ss d c we d c we q16 q32 q48 q64 q16 q32 q48 q64 (output being tested should be in the highlogic state) external power supply i ol v out = v ol v dd = v gs v ss d c we d c we q16 q32 q48 q64 q16 q32 q48 q64 (output being tested should be in the lowlogic state) figure 4. ac test waveforms v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss v dd v ss 50% 12 21617181933 90% 10% t su 16-bit output 1 (15) 17-bit input 32-bit output 6 (10) 33-bit input 48-bit output 2 (14) 49-bit input 64-bit output 5 (11) t h1 t h1 t h1 t h1 t wh t wl t thl t thl t thl t thl v ol v ol v ol v oh v oh v oh 50% 90% 10% 20 ns t rel t phl t phl t phl t phl t plh 90% 10% t tlh t tlh t tlh t tlh t h0 t h0 t h0 t h0 t su0 t su0 t su0 50% 20 ns 20 ns 20 ns v dd v dd v dd t su0 t su1 t su1 t su1 t su1 data in 7 (9) write 3 (13) clock 4 (12) pin no's 90% 10% 50% t plh t plh t plh expanded block diagram (1/2 of device shown) write enable = 0, 16-bit output write enable = 1, 17-bit input clock data write enable 32-bit output 33-bit input 48-bit output 49-bit input 64-bit output high impedance d c 3-state q 32 d c we q 33 d c 3-state q 48 d c we q 49 d c 3-state q 64 d c q 1 d c q 2 d c 3-state q 16 d c we q 17
mc14517b http://onsemi.com 6 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
mc14517b http://onsemi.com 7 package dimensions soic16 dw suffix plastic soic package case 751g03 issue b d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7
mc14517b http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14517b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk
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